word select

module count #(
    parameter DATA_WIDTH=16
) (
    input i_sys_clk,
    input i_sys_rst,
    
    output reg [DATA_WIDTH-1:0] wr_count_o,
    output reg ws_o
);

//Count the number of bits to be transmitted
//It has to be same as the data width
always @ (negedge i_sys_clk or posedge i_sys_rst) begin
    if(i_sys_rst) begin
        wr_count_o <= DATA_WIDTH[1'b0];
    end else begin
        if(wr_count_o == DATA_WIDTH - 1) begin
            wr_count_o <= DATA_WIDTH[1'b0];
        end else begin
            wr_count_o <= wr_count_o + 1;
        end
    end
end

always @ (negedge i_sys_clk or posedge i_sys_rst) begin
    if(i_sys_rst) begin
        ws_o <= 1'b0;
    end else begin
        if(wr_count_o == DATA_WIDTH - 1) begin
            ws_o <= ~ws_o;
        end
    end
end

endmodule

 

TB

`timescale 1ns/1ps

module count_TB();
    reg i_sys_clk;
    reg i_sys_rst;
    wire [15:0] wr_count_o;
    wire ws_o;

    // Instantiate the coount module
    count #(
        .DATA_WIDTH(16)
    ) my_coount (
        .i_sys_clk(i_sys_clk),
        .i_sys_rst(i_sys_rst),
        .wr_count_o(wr_count_o),
        .ws_o(ws_o)
    );

    // Clock generation
    always begin
        #5 i_sys_clk = ~i_sys_clk;
    end

    // Testbench stimulus
    initial begin
        i_sys_clk = 0;
        i_sys_rst = 1;

        // Reset the module
        #10 i_sys_rst = 0;

        // Observe the output for multiple clock cycles
        #350;

        // Finish the simulation
        $finish;
    end
endmodule

sim