[FPGA] 전가산기

전가산기 설계

입력			출력
A	B	Cin	sum	carry
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Design Source

`timescale 1ns / 1ps

module FullAdder(
    input i_a, i_b, i_c,

    output o_sum, o_carry
    );

    wire w_sum_A, w_carry_A, w_carry_B;

    HalfAdder HA0(
    .i_a(i_a),              // .매개변수(입력값)
    .i_b(i_b),
    .o_sum(w_sum_A),          // 선으로 연결  
    .o_carry(w_carry_A)
    );

    HalfAdder HA1(
    .i_a(w_sum_A),
    .i_b(i_c),
    .o_sum(o_sum),
    .o_carry(w_carry_B)
    );

    assign o_carry = w_carry_A | w_carry_B;
endmodule

Schematic

Simulation Source

`timescale 1ns / 1ps

module tb_FullAdder();

    reg i_a, i_b, i_c;
    wire o_sum, o_carry;

    FullAdder dut(
    .i_a(i_a),
    .i_b(i_b),
    .i_c(i_c),
    .o_sum(o_sum),
    .o_carry(o_carry)
    );

    initial begin
        #00 i_a = 1'b0; i_b = 1'b0; i_c = 1'b0;
        #10 i_a = 1'b0; i_b = 1'b0; i_c = 1'b1;
        #10 i_a = 1'b0; i_b = 1'b1; i_c = 1'b0;
        #10 i_a = 1'b0; i_b = 1'b1; i_c = 1'b1;
        #10 i_a = 1'b1; i_b = 1'b0; i_c = 1'b0;
        #10 i_a = 1'b1; i_b = 1'b0; i_c = 1'b1;
        #10 i_a = 1'b1; i_b = 1'b1; i_c = 1'b0;
        #10 i_a = 1'b1; i_b = 1'b1; i_c = 1'b1;
        #10 $finish;
    end

endmodule

 

Timing Chart

 

constraints

## Switches

set_property -dict { PACKAGE_PIN V17  IOSTANDARD LVCMOS33 } [get_ports { i_a }]; #IO_L19N_T3_A09_D25_VREF_14 ,Sch=SW0
set_property -dict { PACKAGE_PIN V16  IOSTANDARD LVCMOS33 } [get_ports { i_b }]; #IO_L19P_T3_A10_D26_14      ,Sch=SW1
set_property -dict { PACKAGE_PIN W16  IOSTANDARD LVCMOS33 } [get_ports { i_c }]; #IO_L20P_T3_A08_D24_14      ,Sch=SW2

## LEDs

set_property -dict { PACKAGE_PIN U16  IOSTANDARD LVCMOS33 } [get_ports { o_sum}]; #IO_L23N_T3_A02_D18_14        ,Sch=LED0
set_property -dict { PACKAGE_PIN E19  IOSTANDARD LVCMOS33 } [get_ports { o_carry}]; #IO_L3N_T0_DQS_EMCCLK_14      ,Sch=LED1

## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

 

전가산기 FPGA 회로 구성

작동사진

i_c = 0, i_b = 0, i_a = 0

i_c = 1, i_b = 0, i_a = 0

i_c = 0, i_b = 1, i_a = 0

i_c = 1, i_b = 1, i_a = 0

i_c = 0, i_b = 0, i_a = 1

i_c = 1, i_b = 0, i_a = 1

i_c = 0, i_b = 1, i_a = 1

i_c = 1, i_b = 1, i_a = 1