[FPGA] 4bit_전가산기

4bit_전가산기 설계

 

Design Source

`timescale 1ns / 1ps

module FullAdder_4bit(
    input [3:0] i_a, i_b,       // i_a[0], i_a[1], i_a[2] ...
    input i_carry_in,
    output [3:0] o_sum,
    output o_carry
    );

    wire w_carry_0, w_carry_1, w_carry_2;

    FullAdder FA0(
    .i_a(i_a[0]),
    .i_b(i_b[0]),
    .i_c(i_carry_in),
    .o_sum(o_sum[0]),
    .o_carry(w_carry_0)
    );

    FullAdder FA1(
    .i_a(i_a[1]),
    .i_b(i_b[1]),
    .i_c(w_carry_0),
    .o_sum(o_sum[1]),
    .o_carry(w_carry_1)
    );

    FullAdder FA2(
    .i_a(i_a[2]),
    .i_b(i_b[2]),
    .i_c(w_carry_1),
    .o_sum(o_sum[2]),
    .o_carry(w_carry_2)
    );

    FullAdder FA3(
    .i_a(i_a[3]),
    .i_b(i_b[3]),
    .i_c(w_carry_2),
    .o_sum(o_sum[3]),
    .o_carry(o_carry)
    );

endmodule

 

Schematic

 

Simulation Source

`timescale 1ns / 1ps

module tb_FullAdder_4bit();
    reg [3:0] i_a, i_b;
    reg i_carry_in;
    wire [3:0] o_sum; 
    wire o_carry;

    FullAdder_4bit dut(
        .i_a(i_a),
        .i_b(i_b),
        .i_carry_in(1'b0),      // 1bit 
        .o_sum(o_sum),
        .o_carry(o_carry)
    );

    initial begin
        #00 i_a = 4'b0000; i_b = 4'b0000;   // 4bit  2
        #10 i_a = 4'd3; i_b = 4'd4;         // 4bit  10
        #10 i_a = 4'ha; i_b = 4'hb;       // 4bit  16
        #10 i_a = 4'd4; i_b = 4'd5;
        #10 i_a = 4'd5; i_b = 4'd6;
        #10 i_a = 4'd6; i_b = 4'd7;
        #10 $finish;
    end
    
endmodule

 

Timing Chart

 

constraints

## Switches

set_property -dict { PACKAGE_PIN V17  IOSTANDARD LVCMOS33 } [get_ports { i_a[0] }]; #IO_L19N_T3_A09_D25_VREF_14 ,Sch=SW0
set_property -dict { PACKAGE_PIN V16  IOSTANDARD LVCMOS33 } [get_ports { i_a[1] }]; #IO_L19P_T3_A10_D26_14      ,Sch=SW1
set_property -dict { PACKAGE_PIN W16  IOSTANDARD LVCMOS33 } [get_ports { i_a[2] }]; #IO_L20P_T3_A08_D24_14      ,Sch=SW2
set_property -dict { PACKAGE_PIN W17  IOSTANDARD LVCMOS33 } [get_ports { i_a[3] }]; #IO_L20N_T3_A07_D23_14      ,Sch=SW3
set_property -dict { PACKAGE_PIN W15  IOSTANDARD LVCMOS33 } [get_ports { i_b[0] }]; #IO_L21N_T3_DQS_A06_D22_14  ,Sch=SW4
set_property -dict { PACKAGE_PIN V15  IOSTANDARD LVCMOS33 } [get_ports { i_b[1] }]; #IO_L21P_T3_DQS_14          ,Sch=SW5
set_property -dict { PACKAGE_PIN W14  IOSTANDARD LVCMOS33 } [get_ports { i_b[2] }]; #IO_L22N_T3_A04_D20_14      ,Sch=SW6
set_property -dict { PACKAGE_PIN W13  IOSTANDARD LVCMOS33 } [get_ports { i_b[3] }]; #IO_L22P_T3_A05_D21_14      ,Sch=SW7
set_property -dict { PACKAGE_PIN R2   IOSTANDARD LVCMOS33 } [get_ports { i_carry_in }]; #IO_L1P_T0_34               ,Sch=SW15

## LEDs

set_property -dict { PACKAGE_PIN U16  IOSTANDARD LVCMOS33 } [get_ports { o_sum[0]}]; #IO_L23N_T3_A02_D18_14        ,Sch=LED0
set_property -dict { PACKAGE_PIN E19  IOSTANDARD LVCMOS33 } [get_ports { o_sum[1]}]; #IO_L3N_T0_DQS_EMCCLK_14      ,Sch=LED1
set_property -dict { PACKAGE_PIN U19  IOSTANDARD LVCMOS33 } [get_ports { o_sum[2]}]; #IO_L15P_T2_DQS_RDWR_B_14     ,Sch=LED2
set_property -dict { PACKAGE_PIN V19  IOSTANDARD LVCMOS33 } [get_ports { o_sum[3]}]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 ,Sch=LED3
set_property -dict { PACKAGE_PIN W18  IOSTANDARD LVCMOS33 } [get_ports { o_carry }]; #IO_L16P_T2_CSI_B_14          ,Sch=LED4

## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

 

4bit_전가산기 FPGA 회로 구성

 

작동사진

(i_b = 4) + (i_a = 3) =  (o_sum = 7)

(i_b = 5) + (i_a = 4) =  (o_sum = 9)

(i_b = 6) + (i_a = 5) =  (o_sum = 11(b))

(i_b = 15) + (i_a = 8) =  (o_sum = 23) -> overflow