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GitHub - kyw6416/FPGA_gates: AND, NAND, OR, NOR, XOR, NOT
AND, NAND, OR, NOR, XOR, NOT. Contribute to kyw6416/FPGA_gates development by creating an account on GitHub.
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Design source
`timescale 1ns / 1ps
module gate(
input i_switch_0,
input i_switch_1,
output o_and, o_nand, o_or, o_nor, o_xor, o_not
);
assign o_and = i_switch_0 & i_switch_1;
assign o_nand = ~(i_switch_0 & i_switch_1);
assign o_or = i_switch_0 | i_switch_1;
assign o_nor = ~(i_switch_0 | i_switch_1);
assign o_xor = i_switch_0 ^ i_switch_1;
assign o_not = ~i_switch_0;
endmodule
schematic
simulation source
`timescale 1ns / 1ps
// Test Bench
module tb_gate();
reg i_switch_0, i_switch_1;
wire o_and, o_nand, o_nor, o_not, o_or, o_xor;
gate dut(
.i_switch_0(i_switch_0),
.i_switch_1(i_switch_1),
.o_and(o_and),
.o_nand(o_nand),
.o_or(o_or),
.o_nor(o_nor),
.o_xor(o_xor),
.o_not(o_not)
);
initial begin
#00 i_switch_0 = 1'b0; i_switch_1 = 1'b0;
#10 i_switch_0 = 1'b0; i_switch_1 = 1'b1;
#10 i_switch_0 = 1'b1; i_switch_1 = 1'b0;
#10 i_switch_0 = 1'b1; i_switch_1 = 1'b1;
#10 $finish;
end
endmodule
timing chart
constraints
## Switches
set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { i_switch_0 }]; #IO_L19N_T3_A09_D25_VREF_14 ,Sch=SW0
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { i_switch_1 }]; #IO_L19P_T3_A10_D26_14 ,Sch=SW1
## LEDs
set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { o_and }]; #IO_L23N_T3_A02_D18_14 ,Sch=LED0
set_property -dict { PACKAGE_PIN E19 IOSTANDARD LVCMOS33 } [get_ports { o_nand }]; #IO_L3N_T0_DQS_EMCCLK_14 ,Sch=LED1
set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { o_or }]; #IO_L15P_T2_DQS_RDWR_B_14 ,Sch=LED2
set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { o_nor }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 ,Sch=LED3
set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { o_xor }]; #IO_L16P_T2_CSI_B_14 ,Sch=LED4
set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { o_not }]; #IO_L23P_T3_A03_D19_14 ,Sch=LED5
## Configuration options, can be used for all designs
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
작동사진
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