FPGA

FND FND 설계 Design Source `timescale 1ns / 1ps module BCDtoFND( input [1:0] i_DigitSelect, input [3:0] i_value, input i_en, output [3:0] o_digit, output [7:0] o_fndFont ); FND_Select_Decoder fndDigitDecoder( .i_DigitSelect(i_DigitSelect), .i_en(i_en), .o_digit(o_digit) ); BCDtoFND_Decoder fndFontDecoder( .i_value(i_value), .i_en(i_en), .o_font(o_fndFont) ); endmodule Schematic Simulation Source `..

디코더? 2X4 디코더 설계 입력 출력 en DigitSelect[1] DigitSelect[0] digit[3] o_digit[2] o_digit[1] o_digit[0] H X X H H H H L 0 0 1 1 1 0 L 0 1 1 1 0 1 L 1 0 1 0 1 1 L 0 0 0 1 1 1 Design Source `timescale 1ns / 1ps // input, output wire 타입이 디폴트 // wire타입은 저장이 안 됨 module FND_Select_Decoder( input [1:0] i_DigitSelect, input i_en, output [3:0] o_digit ); reg [3:0] r_digit; // reg는 메모리 기능 assign o_digit = r_digi..

4bit_가감산기 Design Source `timescale 1ns / 1ps module FullAddersub_4bit( input [3:0] i_a, i_b, input i_mode, output [3:0] o_sum, output o_carry ); wire [3:0] w_b; assign w_b = {4{i_mode}} ^ i_b; // 4는 반복 수 FullAdder_4bit AdderSub( .i_a(i_a), .i_b(w_b), .i_carry_in(i_mode), .o_sum(o_sum), .o_carry(o_carry) ); endmodule Schematic Simulation Source `timescale 1ns / 1ps module tb_FullAddersub_4bit(); ..

4bit_전가산기 설계 Design Source `timescale 1ns / 1ps module FullAdder_4bit( input [3:0] i_a, i_b, // i_a[0], i_a[1], i_a[2] ... input i_carry_in, output [3:0] o_sum, output o_carry ); wire w_carry_0, w_carry_1, w_carry_2; FullAdder FA0( .i_a(i_a[0]), .i_b(i_b[0]), .i_c(i_carry_in), .o_sum(o_sum[0]), .o_carry(w_carry_0) ); FullAdder FA1( .i_a(i_a[1]), .i_b(i_b[1]), .i_c(w_carry_0), .o_sum(o_sum[1]), ...

전가산기 설계 입력 출력 A B Cin sum carry 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Design Source `timescale 1ns / 1ps module FullAdder( input i_a, i_b, i_c, output o_sum, o_carry ); wire w_sum_A, w_carry_A, w_carry_B; HalfAdder HA0( .i_a(i_a), // .매개변수(입력값) .i_b(i_b), .o_sum(w_sum_A), // 선으로 연결 .o_carry(w_carry_A) ); HalfAdder HA1( .i_a(w_sum_A), .i_b(i_c), .o_sum(o_..

반가산기 설계 입력 출력 A B sum carry 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 Design Source `timescale 1ns / 1ps module HalfAdder( input i_a, input i_b, output o_sum, o_carry ); assign o_sum = i_a ^ i_b; // xor assign o_carry = i_a & i_b; // and endmodule Simulation Source `timescale 1ns / 1ps module tb_HalfAdder(); reg i_a, i_b; wire o_sum, o_carry; HalfAdder dut( .i_a(i_a), .i_b(i_b), .o_sum(o_sum), .o_carry(o_..